GDSII

Related by string. * * GDSII design . GDSII flow . GDSII reference *

Related by context. All words. (Click for frequent words.) 71 netlist 71 parasitic extraction 69 RTL synthesis 68 SystemC models 66 Encounter Timing System 66 netlists 66 Magma RTL 65 Synopsys Galaxy 65 UMC #nm 65 datapath 65 DRC LVS 65 Quartz LVS 65 OpenAccess database 65 synthesizable 65 Xilinx FPGA 64 STARCAD CEL 64 TetraMAX 64 Talus Vortex 64 SOPC Builder 64 GDSII flow 63 Cadence Virtuoso 63 TSMC #nm [001] 63 Calibre xRC 63 TSMC AMS 63 VHDL code 62 Cadence Encounter 62 ANSI C 62 Quartz DRC 62 routability 62 eVC 62 Xtensa processor 62 Design Compiler 62 PowerTheater 62 ARM AMBA 62 GDSII design 62 TestKompress 62 CellMath IP 61 IP XACT 61 FPGA prototyping 61 equivalence checking 61 Magma Talus 61 Fast Fourier Transform FFT 61 logic synthesis 61 CoWare Platform Architect 61 DDR PHY 61 ESL synthesis 61 Verilog 61 FPGA 61 EDA tools 61 testbench 61 PowerPro MG 61 PCell 61 IP cores 61 iLVS 61 PrimeTime SI 61 DFT MAX 61 SoC Encounter 61 QRC Extraction 61 tapeout 60 MTCMOS 60 Precision Synthesis 60 FineSim Pro 60 QuickCap NX 60 #:# LVDS 60 PCB layout 60 AXI TM 60 #.# micron CMOS 60 synthesizable IP 60 Synopsys IC Compiler 60 kit PDK 60 parameterized cells 60 Star RCXT TM 60 SPICE simulator 60 PCells 60 Cadence QRC Extraction 60 LEF DEF 60 deep sub micron 60 PyCell 60 Sequence PowerTheater 60 manufacturability DFM 60 SoC 60 ASIC prototyping 60 #.#μm [002] 60 Xtensa processors 59 TSMC Reference Flow 59 Calibre DFM 59 fpgas 59 ISE #.#i 59 IC Compiler 59 Calibre xACT 3D 59 SystemVerilog verification 59 IC Validator 59 deep submicron 59 Synplicity Synplify Pro 59 DesignWare Verification IP 59 parameterized 59 Synplify Premier 59 Olympus SoC 59 testbenches 59 JTAG port 59 SoC designs 59 nm CMOS process 59 Verilog simulation 59 Nios processor 59 Reference Flow 59 AMBA protocol 59 structured ASIC 58 SPICE simulation 58 RealTime Designer 58 chip SoCs 58 RTL simulation 58 synthesizable Verilog 58 iRCX 58 PowerPro CG 58 CustomSim 58 GDSII reference 58 Physical Verification 58 ARM#EJ processor 58 Blast Fusion 58 Quartus II 58 CellMath Designer 58 #nm RF CMOS 58 Altera Quartus II 58 LUTs 58 5V CMOS 58 IBIS AMI models 58 .# micron 58 Star RCXT 58 TSMC #.#um 58 multirate 58 VHDL 58 parasitics 58 QuickCap 58 HSPICE 58 DSP algorithm 58 Calibre LFD 58 FPGA fabric 58 synthesizable RTL 58 #.#μm CMOS 58 YieldAssist 58 coprocessing 58 nanoPHY 58 serdes 58 iPDK 58 ECSM 58 Mentor Calibre 57 System Verilog 57 algorithmic synthesis 57 OpenAccess 57 RFIC design 57 SAR ADC 57 MicroBlaze 57 SiliconSmart 57 Synopsys Design Compiler 57 schematic capture 57 CMOS compatible 57 Catapult C 57 Atrenta SpyGlass 57 computational lithography 57 Stratix III FPGAs 57 EM simulation 57 Talus Design 57 ispLEVER 57 nanoPHY IP 57 Xilinx ISE 57 SMIC #.#um 57 PCIe Gen2 57 Panasas storage 57 #nm CMOS [001] 57 Solido Variation Designer 57 datapaths 57 TSMC #nm process 57 Talus RTL 57 CMOS logic 57 OrCAD 57 boundary scan 57 TRF# [002] 57 BIST 57 FineSim SPICE 57 Forte Cynthesizer 57 OpenDFM 57 synchronous Ethernet 57 Blast Create 57 Cortex M1 57 SPI#.# 57 Custom Designer 57 NanoSim 57 Synplify DSP 57 #MS s [002] 57 UMC #.#um 57 Encounter RTL Compiler 57 PLLs 56 PICO Extreme 56 serializer 56 XSL FO 56 PyCells 56 CellMath 56 SystemC 56 chip variation OCV 56 encoding decoding 56 VisualSim 56 Serdes 56 AMBA AXI 56 Fast SPICE 56 HCS# 56 daughtercards 56 PHY layer 56 TetraMAX ATPG 56 MEGACO 56 Cadence Encounter digital 56 RTL Compiler 56 Cadence Allegro 56 logic CMOS 56 SFP + modules 56 logic analyzer 56 Nios II 56 Synopsys PrimeTime 56 #/#nm 56 Java bytecode 56 IPexpress 56 Parasitic Extraction 56 customizable dataplane processor 56 FPGA prototypes 56 TSMC Nexsys 56 Virtex 5 56 Verilog RTL 56 Reference Methodology 56 LTE UE 56 TCP IP networking 56 AXI4 56 nm CMOS 56 SLIMbus 56 DFM DFY 56 decoupling capacitance 56 Esterel Studio 56 ARM#EJ S 56 bit RISC processor 56 adaptive equalization 56 DesignWare IP 56 #nm silicon 56 XSLT transformations 56 NOR NAND 56 ADCs DACs 56 clock gating 56 SiWare 56 ZenTime 56 Synplify Pro 56 HIT Kit 56 serializer deserializer 56 PSpice 56 Actel FPGA 56 CoolTime 56 DAC# 56 SpyGlass Power 56 RET OPC 55 QoR 55 voltage CMOS 55 bytecodes 55 AT#SAM# [002] 55 Active HDL 55 HyperLynx 55 Synopsys VCS 55 Libero IDE 55 BiCMOS 55 Evaluation Module 55 ispLEVER design 55 Cadence Virtuoso custom 55 DesignWare USB 55 PDKs 55 Xilinx Spartan 3A 55 jitter attenuation 55 1Mbyte 55 FBDIMM 55 Magma Blast 55 level synthesis HLS 55 HardCopy II 55 #nm SoC 55 XSLT stylesheets 55 Texas Instruments OMAP# 55 datatypes 55 memory BIST 55 sequential clock gating 55 multichip 55 PHY interfaces 55 NetX Duo 55 ModelSim 55 #nm/#nm 55 Actel Fusion 55 iPDKs 55 digital isolator 55 ARM# [003] 55 Stratix III 55 Stratix IV FPGA 55 GZIP 55 mask ROM 55 ARM Artisan 55 coprocessor 55 ASIC SoC 55 DPOJET 55 PICO Express 55 DPLL 55 #nm LL 55 DFT Compiler 55 embOS 55 #v# [004] 55 design kits PDKs 55 IC CAP 55 Cadence Virtuoso ® 55 #nm #nm [004] 55 ConvergenSC 55 Power Format UPF 55 Specman Elite 55 external EEPROM 55 #Gbit [001] 55 Manufacturability 55 downconverter 55 PIC microcontroller 55 PyCell Studio 55 Application Specific 55 Cadence SoC Encounter 55 SPI interface 55 Xilinx ML# 55 results QoR 55 MMAV 55 executable specification 55 ATopTech 55 Altera FPGAs 55 AutoCAD DWG 55 WiCkeD 55 Databahn 55 ZeBu 55 nanometer nm 55 GLOBALFOUNDRIES #nm 55 Altera Stratix II 55 #nm CMOS [002] 55 lithography simulation 55 Cadence Incisive 55 nanometer CMOS 55 Synplify 55 #nm node [002] 55 ASIC FPGA 55 IEEE#.# [002] 55 LVDS outputs 55 Synopsys DesignWare 55 MicroBlaze soft processor 55 SPICE simulators 55 ZMD# 55 Calibre nmDRC 55 SignalExpress 55 SCE MI 55 SystemWeaver 55 uPD# [001] 55 DSP Builder 55 RTL verification 55 GoldTime 55 SERDES 55 complex SoC designs 55 SRIO 55 waveform generator 55 Cadence Encounter RTL Compiler 55 matrix multiplication 55 RFCMOS 55 IBIS AMI 55 Freescale MSC# 55 fast Fourier transform 55 LVCMOS 55 AVR ONE 55 uC 55 MirrorBit Eclipse 55 Design Kits 55 FPGAs 55 Arria GX FPGAs 55 AccelWare 55 XSD 55 Agilent ADS 55 Lauterbach TRACE# 55 6Gbps SAS 54 Zroute 54 SPICE accuracy 54 AXIe 54 PowerPro Analyzer 54 SAS expanders 54 Allegro PCB 54 CoreMP7 54 HardCopy ASIC 54 FIFOs 54 Incisive Enterprise 54 Mali# [002] 54 SystemC TLM 54 PHY# [001] 54 VMM methodology 54 libraries IPs 54 ATmega#P [001] 54 floorplanning 54 partial reconfiguration 54 RapidChip 54 CMOS RF transceiver 54 TC#XBG 54 IXP# [001] 54 PSoC Designer 54 fully synthesizable 54 #Kbyte [002] 54 Cynthesizer 54 ASICs 54 Silego 54 SerDes 54 #.#μm CMOS process 54 ChipScope Pro 54 QDRII 54 respins 54 CoFluent Studio 54 DVB ASI 54 Impinj AEON 54 PSoC Creator 54 geometry shaders 54 PCI Express Gen2 54 compiler optimizations 54 TMS#DM# [002] 54 pinout 54 ARM7TDMI processor 54 T1 E1 54 VR#.# 54 #nm [001] 54 Cortex M4 processor 54 Verilog VHDL 54 #K CPS 54 multi Vdd 54 RLDRAM II 54 interposer 54 AWR Microwave Office 54 Anirudh Devgan general 54 XRT#L# 54 Xilinx FPGAs 54 memory compilers 54 Open Verification Methodology 54 Synopsys DesignWare ® 54 CoWare SystemC 54 RedHawk SDL 54 Stratix II FPGA 54 termination resistors 54 Stratix II 54 interoperable PDK 54 Mentor Questa 54 J BERT 54 virtual prototyping 54 FB DIMM 54 VHDL Verilog 54 PCIe 54 Power Format CPF 54 SystemRDL 54 synchronous buck converter 54 MPC#E 54 IO Link 54 PSoC Express 54 Quartus II software 54 multithread 54 L2 L7 54 DM# [001] 54 SoCs ASICs 54 VarioTAP ® 54 8bit MCU 54 PureSpec 54 Simulink models 54 Theseus Titanium 54 #.#ac 54 CST MWS 54 MCMM 54 VarioTAP 54 RXAUI 54 #nm 1Gb 54 DM#x [002] 54 AVR# [002] 54 multibit 54 PXIe 54 SystemC modeling 54 Actel ProASIC3 54 #bit MCUs 54 Stratix II GX FPGA 54 LatticeECP2M 54 TMS#DM# [001] 54 deserializer 54 FPGA ASIC 54 RISC microprocessor 54 Verification Methodology Manual VMM 54 XAUI 54 multiprocessor 54 Encounter Conformal Constraint Designer 54 DXF file 54 SpyGlass ® 54 ARM9 core 54 nanometer silicon 54 serializer deserializer SerDes 54 AVR microcontrollers 54 Synplify Pro software 54 FPDP 54 inductor synthesis 54 Intelli DDR3 54 reconfigurable logic 54 Fractional N 54 Cadence Silicon Realization 54 MoSys 1T SRAM 54 Altera FPGA 54 ACCELLERANT 54 #.# micron node 54 LX#T FPGA 54 Xtensa LX 54 multicore DSPs 54 RFIC simulation 54 Premal Buch general 54 JESD# [002] 54 DMOS 54 MicroBlaze processor 54 ARM# [001] 54 Fusion MPT 54 interposers 54 Magma Quartz 54 PCI Express PHY 54 #LP [002] 54 demodulation 54 PowerShell commands 54 RTL Synthesis 54 MOS transistors 54 toolpath generation 54 DongbuAnam 53 nanometer nm CMOS 53 Memory Controllers 53 eNB 53 Verilog SystemVerilog 53 SiliconSmart ACE 53 MathWorks Simulink 53 parametric 53 #/#-nm 53 Actel FPGAs 53 chip SoC 53 MIPS# #K 53 custom ASICs 53 UML SysML 53 AT#C# [001] 53 JPEG# compression 53 DesignWare DDR 53 Silicon Realization 53 SoCs 53 ADC DAC 53 EEPROM emulation 53 SystemVue 53 CAP7 53 PECL 53 DWG DXF 53 Tessent 53 schematics layout 53 Flash MCU 53 RealView SoC Designer 53 #b/#b encoding 53 CAD geometry 53 Level Synthesis 53 #nm SOI 53 Native Testbench 53 wirebond 53 Ultra DMA 53 RISC DSP 53 SATA Revision #.# 53 Agilent DisplayPort 53 C Compiler 53 ARM Cortex M3 53 Apache RedHawk 53 Mentor Graphics Calibre 53 U3D 53 Ansoft Designer 53 XML parser 53 #Msps [002] 53 Stratix II GX 53 DDR3 RDIMM 53 I2C SPI 53 HSPICE R 53 NI TestStand 53 SoC designers 53 PID loop 53 baseband MAC 53 IEEE #.# [002] 53 Compact PCI 53 #.#um [002] 53 InCyte 53 embedded EEPROM 53 ML#Q# 53 NanoTime 53 LogiCORE IP 53 XFP module 53 ActiveDesign 53 Cortex M1 processor 53 reconfigurability 53 anti aliasing filters 53 multiple CPU cores 53 #.#μ 53 DDR2 SODIMM 53 kit RDK 53 FPGA CPLD 53 MIPS# architecture 53 baseband processing 53 CS# [002] 53 PHYs 53 C#x DSPs [001] 53 PXI Express 53 wph 53 CPLD 53 JTAG emulator 53 cmos 53 Structured ASICs 53 DDR2 memory interface 53 CoWare ConvergenSC 53 SynTest 53 ANSYS POLYFLOW 53 Verilog HDL 53 Virage Logic SiWare 53 RealView Profiler 53 DDR Memory 53 simultaneous multithreading 53 Virtuoso IC 53 F3D 53 MIPS processor 53 SystemVerilog 53 arrays FPGA 53 downconverting 53 SRAM DRAM 53 CircuitSpace 53 IP Cores 53 compiler debugger 53 OSCI TLM 53 HSIM 53 VTOC 53 interprocessor communication 53 debug 53 Virtuoso Multi 53 AccelChip 53 Peripheral Component Interconnect 53 PRBS 53 MPC#E processor 53 PCI Express 53 nano imprint 53 NeoKicks 53 frequency dividers 53 Talus Vortex FX 53 Configurable Logic 53 FPGA DSP 53 Structured eASIC 53 high voltage BCDMOS 53 #G DQPSK 53 CoWare ESL 53 XPM 53 SiP 53 Aprisa 53 SignalMeister software 53 Zarlink ZL# 53 Industry Highest Density 53 CS#L# 53 reticle enhancement 53 microcode 53 AMBA ® 53 modulation formats 53 RFC# 53 backplane connector 53 #Kf 53 iSCSI protocol 53 APP# [002] 53 Synopsys DFM 53 SIwave 53 silicon interposer 53 CHIPit 53 #Kbytes [002] 53 Mixed Signal IC 53 nm nodes 53 Bezier curves 53 8G Fibre Channel 53 AMS RF 53 cache coherency 53 FlexPhase 53 SIMD instructions 53 Ethernet AVB 53 arbitrary waveform generators 53 IPv#/IPv# 53 DALiM TWiST 53 Denali Blueprint 53 Stratix II FPGAs 53 Digital Converter ADC 53 decoupling capacitors 53 DFEB 52 AWG# 52 AccelArray 52 HSPICE ® 52 waveform analyzer 52 XMC module 52 TAS# [001] 52 VESA DisplayPort 52 equivalence checker 52 iRCX format 52 ARM RealView 52 demux 52 Agilent B#A 52 XPath expressions 52 MATLAB algorithms 52 locked loop PLL 52 AMBA interconnect 52 H.#/MPEG-# AVC 52 #Mbyte [001] 52 AT#C# [002] 52 scales linearly 52 upconverters 52 SBC# [003] 52 relational OLAP 52 Photolithography 52 Tensilica Xtensa 52 eDRAM 52 Incentia 52 XML parsing 52 Customizable Microcontroller 52 MapForce 52 IC Compiler #.# 52 LatticeECP2 M 52 eSi 52 PCI Express specification 52 vNIC 52 PowerCentric 52 Aceplorer 52 asynchronous SRAM 52 Analog Mixed Signal 52 MOS transistor 52 AccelDSP 52 QDRII + 52 MI #XM 52 RapID Platform 52 OpenEXR 52 digitisers 52 #.#V CMOS 52 DDR NAND 52 LSI MegaRAID 52 #G OTN [001] 52 Mbit SRAMs 52 L1 cache 52 H.# VC 1 52 Agilent #A [001] 52 MegaCore 52 Cortex A8 processor 52 2eSST 52 correction OPC 52 OpenGL ES #.#/#.# 52 programmable logic devices 52 Boundary Scan 52 workcell 52 parametrics 52 #nm #nm [005] 52 x8 PCI Express 52 RedHawk Linux 52 ARM#EJ S TM 52 MCP# AFE 52 #nm NAND flash 52 Electronic Dispersion Compensation 52 Simucad 52 Virtuoso Accelerated Parallel Simulator 52 RS# interface 52 DDR1 52 Design Compiler Graphical 52 MPEG2 TS 52 Altera Cyclone III 52 Measurement Studio 52 EP#S# 52 Synphony HLS 52 Encounter Conformal 52 Incisive ® 52 arbitrary waveform 52 FPGA synthesis tools 52 NexusRoute 52 PeakView 52 uCLinux 52 powerline modem 52 Trueflow SE 52 SMIC #nm 52 Cadence Encounter Digital 52 #nm FPGAs 52 XA Spartan 3A 52 linearisation 52 ARChitect 52 LQFP package 52 PHY 52 AFS Nano 52 ASICs FPGAs 52 Atmel AVR# 52 Sonet SDH 52 Synopsys DesignWare USB 52 2Xnm 52 4Gb DDR3 52 Agilent J BERT 52 RS#/RS# 52 #GB DDR3 52 6WINDGate 52 ULPI 52 pin BGA package 52 FPGA synthesis 52 HDL simulator 52 OutPerform 52 Verification IP 52 ATPG 52 PureTime 52 ARM# MPCore processor 52 parameterization 52 parallelization 52 iWARP 52 TCI# 52 ARM#J S 52 HKMG technology 52 picoChip PC# [002] 52 I2C interface 52 Xtensa LX processor 52 pipelined architecture 52 chip SoC designs 52 computationally efficient 52 spiral inductors 52 AMBA AHB 52 ISO# 6B 52 lowpass filter 52 curve tracer 52 Host Controller 52 BLDC motor 52 LGS 3D 52 bit PIC# MCUs 52 ARM7 52 SFP + optical 52 programmable MTP 52 through silicon vias 52 Logic Analyzer 52 microcontroller subsystem 52 Logic Navigator 52 ExtremeFFS 52 pHEMT 52 #.#u 52 Gbits s 52 SOI CMOS 52 IAR KickStart Kit 52 nvSRAM 52 DfM 52 STIL 52 FloTHERM 52 M#K 52 MIPS cores 52 Sourcery + 52 baseband LSI 52 FPGA architectures 52 IEEE #.# standard 52 x4 PCI Express 52 DesignWare Verification Library 52 JSON JavaScript Object Notation 52 #bit ADC 52 DQPSK 52 planarization 52 O subsystem 52 JSPs 52 DDR/DDR2 52 Nexxim 52 raster images 52 SiT# 52 CMOS oscillators 52 3G SDI 52 #MIPS [002] 52 PIC#F# [002] 52 TMDS 52 Logical Volume Manager 52 Application Specific Extension 52 QualiPHY 52 DXF files 52 Preconfigured 52 #nm immersion lithography 52 analog circuits 52 differential LVPECL 52 checksum 52 SigmaQuad 52 ProASIC Plus 52 Teja NP 52 SATA AHCI 52 #Kbit [001] 52 bipolar transistors 52 DDR memory 52 ATTO Disk Benchmark 52 #/#bit 52 Magillem 52 multi threaded architecture 52 MDIO 52 RedHawk NX 52 Mixed Signal Design 52 ARM#E 52 SoC Designer 52 #bit CPU 52 optimizations 52 uC TCP IP 52 MB#C# [001] 52 BEOL 52 MirrorBit ORNAND 52 SiGe bipolar 52 DTDs 52 jitter tolerance 52 Multithreaded 52 #.#Gbps [003] 52 AllOnHost 52 flowcharting 52 Multi threading 52 HKMG 52 PLL Noise Analyzer 52 Verification Methodology 52 prefetch 52 HeartOS 52 SFN#F 52 1GB PC# 52 graphical debugging 52 Tcl 52 serialiser 52 TVP# 52 Nios II processor 52 LatticeEC 52 Stratix IV 52 TTL CMOS 52 #bit [001] 52 ZeBu Server 52 NFP #xx 52 Prover eCheck 51 linearization 51 #Mbyte [002] 51 capacitances 51 PNX# 51 PIC#F# [001] 51 XML Schema 51 Macraigor 51 N#B [001] 51 MQX RTOS 51 EVE ZeBu 51 Nuvoton 51 OPC UA 51 smaller geometries 51 BSDL 51 MAX# integrates 51 postprocessing 51 mask reconfigurable 51 raster image 51 configurable 51 BitWackr 51 MODBUS RTU 51 CryptoMemory 51 SystemC transaction 51 PHY IP 51 CHAINworks 51 TMS#C#x + 51 ARM#JZF S processor 51 ownership CoO 51 #nm lithography [002] 51 SoC verification 51 SFP + module 51 RocketDrive 51 Memory Controller 51 MachXO 51 Xilinx ISE Design 51 MDDL 51 MPEG decoder 51 4KEc 51 FPGAView 51 pulse width modulation 51 SGMII 51 LQFP# [001] 51 DSP FPGA 51 VPX backplane 51 eRM 51 USART 51 SOAP messages 51 CMOS transistors 51 #nm MirrorBit 51 e# cores 51 hardware accelerators 51 JavaScript DOM 51 ARM CoreSight 51 ARM#JF S 51 PSoC architecture 51 LVCMOS LVTTL 51 FXT FPGAs 51 Tensilica cores 51 JFET 51 multi gigabit transceivers 51 AutoCAD MicroStation 51 RISC processor 51 HardCopy 51 nonvolatile memory NVM 51 FPGAView software 51 Embedded DRAM 51 tapeouts 51 SystemC synthesis 51 DAPDNA 51 polar modulation 51 PolarPro II 51 OpenIB software 51 IQ modulator 51 Structured ASIC 51 RAID adapters 51 H.# Codec 51 dsPIC#F# 51 evaluation module EVM

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