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(Click for frequent words.) 64 deterministically 58 parameterized 58 determinism 57 nondeterministic 57 nonlinear 57 deterministic latency 55 stateful 55 asynchronous 55 testbenches 55 interrupt latency 54 SPICE accurate 54 SystemC models 54 datapath 54 fast Fourier transform 53 topology 53 parallelization 53 combinatorial optimization 53 connectionless 53 Deterministic 52 packetization 52 jitter attenuation 52 computationally efficient 52 symmetric multiprocessing 52 netlists 52 SERCOS III 52 Iub 52 packet forwarding 52 Talus Vortex 51 linear 51 Spanning Tree 51 latency packet 51 finite element method 51 nonlinear dynamics 51 optimality 51 reconfigurability 51 multithread 51 multirate 51 Vdd 51 topological 51 jitter 51 parameterization 51 parallelism 51 dynamically configurable 51 parallelized 51 monotonic 51 impedances 51 μs 51 probabilistic 51 invariants 51 multi threaded 51 worstcase 51 linearly scalable 51 symmetric 50 fault tolerant 50 adaptive equalization 50 Asynchronous 50 Bayesian 50 bursty 50 gigabit serial 50 architectures 50 routing protocols 50 hardware accelerators 50 Frequency Shift Keying 50 failovers 50 TCP IP networking 50 netlist 50 FIFOs 50 ANSI C 50 RSTP 50 DDR PHY 50 parasitic extraction 50 sub microsecond 50 chip variation OCV 50 parametric 50 network topology 50 multi threaded architecture 50 simulated annealing 50 Ethernet Powerlink 50 Symmetric Multiprocessing SMP 50 programmable 49 recursive 49 nonzero 49 identical waveforms 49 scalar 49 O subsystem 49 QoS 49 SyncE 49 synchronous 49 Bayesian inference 49 mutexes 49 PID loop 49 cache coherency 49 multiprocessor 49 equilibria 49 ideality 49 TCP UDP 49 RTLinux 49 MTCMOS 49 L2 L7 49 reconfigurable logic 49 computationally intensive 49 testable 49 computational algorithms 49 Schrodinger equation 49 priori 49 teleological 49 SystemVerilog verification 49 SPICE simulation 49 FPGA fabric 49 DSP architectures 49 latencies 49 LVCMOS LVTTL 49 emulation 49 nonblocking 49 CustomSim 49 scales linearly 49 RISC processor 49 linearity 49 eigenvalues 48 metastability 48 RISC microprocessor 48 synchronization primitives 48 SPICE accuracy 48 diffusive 48 Gaussian 48 stochastic simulation 48 intertemporal 48 AMBA interconnect 48 heterogeneous multicore 48 instantiation 48 multi Vdd 48 hierarchical 48 #μs [002] 48 Cadence Encounter Test 48 testbench 48 self calibrating 48 pseudorandom 48 hysteresis 48 asynchronous messaging 48 linear scalability 48 asymmetric multiprocessing 48 automatable 48 wirespeed 48 observability 48 #ns [002] 48 reconfigurable 48 interprocess communications 48 dataflow 48 interprocessor communications 48 Fast SPICE 48 JTAG port 48 decoherence 48 modulation schemes 48 multigigabit 48 #.#Gb s [002] 48 Verilog simulation 48 datarates 48 packet filtering 48 FineSim Pro 48 compiler optimizations 47 VHDL Verilog 47 timestamping 47 dataplane 47 multipathing 47 hierarchically organized 47 Cadence Encounter 47 SystemC modeling 47 VarioTAP ® 47 synthesizable 47 adiabatic 47 multiprocessing 47 vNIC 47 abstraction 47 linearized 47 realtime 47 empirically testable 47 ADCs DACs 47 sine cosine 47 heterogeneous architectures 47 deterministic jitter 47 programmability 47 packet jitter 47 reconfigurable computing 47 dissipative 47 RNGs 47 HSIM 47 reconfigurable hardware 47 instantiates 47 dephasing 47 FPGA prototyping 47 interprocessor communication 47 interleaving 47 interprocess communication 47 nonlinearities 47 TCP optimization 47 multi pathing 47 clockless 47 PHY layer 47 Fast Fourier Transform FFT 47 serdes 47 coprocessing 47 recursion 47 Concurrent RedHawk Linux 47 scale linearly 47 #MIPS [002] 47 JavaBeans 47 GDSII flow 47 SPICE simulators 47 propositional 47 multicore 47 multicore architectures 47 optimization algorithms 47 anthropic 47 thermodynamic 47 rasterization 47 clock gating 47 serializer deserializer 47 XAUI 47 User Datagram Protocol 47 multithreading 47 latency jitter 47 IMS TISPAN 47 interoperation 47 TCP protocol 47 bidirectional 47 reprogrammable 47 gravitational redshift 47 TCP multiplexing 47 frequency dividers 47 load balancing 47 PLLs 47 Schrödinger equation 47 loopbacks 47 QoS Quality 47 prefetch 47 ferromagnetic materials 47 Xtensa processors 47 IO Link 47 interfaces 47 QoR 47 spatio temporal 47 async 47 Ethernet TCP IP 47 SystemC TLM 47 MathWorks Simulink 47 computationally intense 47 Bayesian probability 46 stochastic optimization 46 fanout 46 determinist 46 computationally expensive 46 parallelizing 46 repeatable 46 parasitics 46 arbitrary waveforms 46 multithreaded 46 parametric modeling 46 nonlinearity 46 computing architectures 46 GZIP compression 46 mesh topology 46 theoretic 46 modulo 46 frameshift 46 interpretable 46 deterministic Ethernet 46 Service QoS 46 nonequilibrium 46 VarioTAP 46 massively parallelized 46 asymptotically 46 remoting 46 debugging 46 lambdas 46 RISC architecture 46 output capacitance 46 Gbits s 46 multibit 46 Carrier Grade RTLinux 46 Maxwell equations 46 SSL offloading 46 eigenvalue 46 spatio 46 Amdahl Law 46 datastore 46 OpenAccess database 46 FPGA 46 encoding decoding 46 multinomial 46 serial interfaces 46 symmetric multiprocessing SMP 46 OSEck 46 HSPICE 46 network topologies 46 servo loop 46 subsecond 46 programmable DSPs 46 baud rate 46 testability 46 O MPIO 46 TCP IP protocol 46 modulation formats 46 SPICE simulator 46 SDH SONET 46 RTL synthesis 46 Nios II Compiler 46 multi threading 46 IPsec 46 lognormal 46 Mendelian inheritance 46 RELAX NG 46 CoWare Platform Architect 46 logics 46 perturbation theory 46 binary 46 NanoTime 46 concatenation 46 threshold voltages 46 ADRES 46 algorithms 46 topologies 46 Gaussian distribution 46 fieldbuses 46 immutability 46 Probabilistic 46 Multipath 46 Rapid Spanning Tree 46 serializer 46 recursive queries 46 inverse kinematics 46 microsecond 46 CPU utilization 46 IPv4 IPv6 46 unoptimized 46 Configurable 46 multipath fading 46 TTL compatible 46 instantiations 46 EM simulation 46 CABAC 46 #.#ns 46 deep sub micron 46 Ethernet MACs 46 decoupling capacitance 46 loopback mode 46 decompilation 46 associative arrays 46 EtherCAT 46 picoseconds ps 46 reproducible 46 sub millisecond 46 multiply accumulate 46 instantiated 46 logic 46 #.#Gbps [001] 46 RDBMSs 46 RTCore 46 #v# [004] 46 OSNR 46 jitter packet loss 46 deep submicron 46 IPv#/IPv# 46 ratiometric 46 invariant 46 msec 46 mathematical formalism 46 LabVIEW graphical programming 46 memory subsystem 46 Xtensa LX processor 46 I2C interface 46 datatypes 46 synthesis 46 Quiescent current 46 debugging tools 45 #BASE T [001] 45 packet switched 45 GMSK 45 MediaLB 45 ASIC prototyping 45 SAR ADC 45 observable phenomena 45 Recursive 45 FastSPICE 45 Boolean 45 AVR MCU 45 PCIe GbE 45 automated failover 45 MILS architecture 45 cluster nodes 45 impedance measurements 45 LatticeECP2 M 45 multiprocessors 45 characteristic impedance 45 external resistor 45 FDTD 45 RedHawk Linux 45 configurable 45 SystemWeaver 45 Multithreaded 45 Monte Carlo simulation 45 gaussian 45 Quantum entanglement 45 stateful failover 45 synchronous replication 45 Verilog RTL 45 computational 45 TCP IP 45 quaternion 45 variational 45 SGMII 45 XML parser 45 jitter buffer 45 numerics 45 bistability 45 #.#Gbps [003] 45 Parallelism 45 IEEE #v# 45 sFlow 45 heterogeneous 45 infinite scalability 45 intrinsic jitter 45 LXI instruments 45 Boolean logic 45 isochronous 45 optimized 45 superpositions 45 memory BIST 45 Design Compiler 45 logic synthesis 45 datarate 45 multicore CPU 45 lattice QCD 45 RTL simulation 45 dialectical materialist 45 compiler debugger 45 Xilinx FPGA 45 VPX backplane 45 latency 45 Mendelian 45 AXI TM 45 Stratix II FPGA 45 SIMD 45 constraint solver 45 matrix multiplication 45 neurally 45 binary compatibility 45 pleiotropy 45 parameter estimation 45 processive 45 Euclidean 45 DMIPS 45 atomicity 45 codeless 45 accelerator emulator 45 Cortex M3 core 45 PWM pulse width modulation 45 ISE #.#i 45 PHY interfaces 45 heuristics 45 interleaved 45 AMBA AXI 45 PCell 45 atomistic 45 Platonic solids 45 bounded rationality 45 equivalence checking 45 multiplexing 45 pixel shading 45 TimeMachine ™ 45 #Base T [003] 45 adaptive modulation 45 Serdes 45 finer granularity 45 Hysteresis 45 initialization 45 iterator 45 RC oscillator 45 DSP algorithm 45 sRIO 45 PCIe Gen2 45 CoFluent Studio 45 fpgas 45 VisualSim 45 asymptotic 45 oscillatory 45 ZSN 45 cfengine 45 probabilistic reasoning 45 XML parsing 45 spatial temporal 45 1ms 45 parallel kinematics 45 protocol agnostic 45 #Gbps serial 45 factorization 45 BIST 45 highly parallelized 45 multiplexer demultiplexer 45 Force# switches 45 vApps 45 multi threaded applications 45 TI TMS#DM#x 45 dynamically adjusts 45 routability 45 equivalence checker 45 RSA#B 45 trigonometric 45 GDSII 45 #Base T [002] 45 IBIS AMI 45 evolvability 45 RFC# 45 frequency synthesizers 45 graphical debugging 45 multibody 45 I2C bus 45 jitter measurement 45 iterative 45 statistical inference 45 inputs outputs 45 MODBUS RTU 45 electron tunneling 45 vectorial 45 MIPS processors 45 PowerPro CG 45 NeoKicks 45 quantum bits qubits 45 mechanistic 45 coplanar 45 Kaminario K2 45 quantum computation 45 sigma delta modulator 44 oscillator frequency 44 galvanically isolated 44 WiMedia compliant 44 electromigration 44 IPv#/IPv# routing 44 rhythmicity 44 RISC CPU 44 quantization 44 multihop 44 datapaths 44 pulse width modulation 44 wavefunction 44 synthesizable Verilog 44 performant 44 checkpointing 44 extensible 44 debug 44 OpenMP 44 instrumentation amplifier 44 voltages 44 Einstein equations 44 TTL CMOS 44 compression caching 44 unfalsifiable 44 Netflow 44 galvanic isolation 44 geometric modeling 44 demodulation 44 Monte Carlo simulations 44 SERDES 44 differential signaling LVDS 44 multi gigabit transceivers 44 initialisation 44 fine grained 44 HardCopy II 44 lowpass filter 44 MEGACO 44 VHDL AMS 44 timebase 44 converters ADC 44 bi directional 44 fault tolerant architecture 44 abstraction layers 44 inferential statistics 44 instantiating 44 C#x + DSP 44 MIPS CPU 44 algorithmic synthesis 44 quantum mechanically 44 chemical kinetics 44 DiffServ 44 TetraMAX 44 complier 44 Olympus SoC 44 loopback 44 #BASE TX 44 Heisenberg principle 44 TDR TDT 44 spatiotemporal 44 SH 4A 44 NMR experiments 44 multi gigabit 44 combinatorial 44 +5 dBm 44 ViewState 44 CoDeSys 44 FPGAs 44 parametrics 44 arrays FPGAs 44 Load balancing 44 DDR2 memory interface 44 Master Slave 44 termination resistors 44 mesoscopic 44 Fourier transforms 44 Dirac equation 44 heuristic 44 thermodynamic equilibrium 44 synthesizable RTL 44 VLANs 44 adjoint 44 aperiodic 44 LVTTL 44 falsifiability 44 cardinality 44 ARM7 44 isomorphic 44 overtemperature protection 44 unicast 44 RASER 44 TMS#DM# [002] 44 malloc 44 ModelSim 44 SIMD instructions 44 syllogisms 44 microsecond latency 44 NIST quantum 44 #b/#b encoding 44 PowerPro MG 44 Xilinx ISE 44 datapath designs 44 compute nodes 44 dynamical systems 44 Simulink models 44 symmetric encryption 44 combinational 44 multi homed 44 Intel Wireless MMX2 44 programmable shaders 44 Cortex R4 processor 44 multichassis 44 MathWorks MATLAB 44 Sonet SDH 44 low latency 44 DTDs 44 Nios II processor 44 μsec 44 compute intensive tasks 44 OFDM orthogonal frequency 44 WPANs 44 subroutine 44 memory compilers 44 baselining 44 rotary encoder 44 SOAP XML 44 binary code 44 Force# C# 44 Mitrion C 44 computationally 44 LVPECL LVDS 44 SPI interface 44 ACCELLERANT 44 Altera Quartus II 44 XMEGA 44 CoreMP7 44 synchronous Ethernet 44 Encounter Conformal Constraint Designer 44 #.#V #.#V [002] 44 Gbps throughput 44 multicore CPUs 44 multiprocessor systems 44 demultiplexing 44 Gbps InfiniBand 44 analog circuitry 44 waveform generator 44 Boundary Scan 44 simultaneous multithreading 44 RISC cores 44 NVRAM 44 MPEG2 TS 44 curve tracer 44 tuple 44 Stratix IV FPGA 44 DQPSK 44 Signaling Analyzer 44 deductive logic 44 hardwired 44 PurePath 44 waveform viewer 44 probabilistic modeling 44 DiSEqC 44 circuit emulation 44 manycore 44 IBIS AMI models 44 falsifiable 44 LVPECL 44 DFT calculations 44 revisable 44 MOS transistor 44 endian 44 ITU T Y.# 44 Kbits 44 Virtual Machine VM 44 electrically noisy 44 polarization multiplexed 44 encryption decryption 44 ActiveRecord 44 microsecond latencies 44 transconductance 44 ARM# [001] 44 programming OOP 44 ISAKMP 44 stochasticity 44 MicroBlaze processor 44 theoretical 44 bytecodes 44 sensors actuators 44 muxing 44 subjectivist 44 enthalpy 44 associativity 44 Link OAM 44 PID loops 44 DSPs FPGAs 44 #GFC 44 ± #V [002] 44 cacheable 44 JVMs 44 scalable 44 dynamically adapt 44 ontological 44 nanoWatt Technology 44 fuzzy logic 44 windowing 44 sub millisecond latency 44 #bit [001] 44 bidirectional communication 44 Xtensa processor 44 object relational 44 datatype 44 #.#GB/sec [002] 44 SiliconSmart 44 termination resistor 44 CAN LIN 43 EEMBC benchmarks 43 1Mbyte 43 SOAP HTTP 43 nsec 43 UDP TCP 43 Harmonic encoders 43 #μs [001] 43 Hierarchical 43 RealView Profiler 43 meiotic recombination 43 Viterbi decoder 43 MPC#E processor 43 linear progression 43 additive jitter 43 CFD solvers 43 analog waveform 43 PHY# [001] 43 parameterised 43 mathematical notation 43 Einsteinian 43 nanoseconds ns 43 PSRR 43 failover clustering 43 bi directional communication 43 relativistic 43 parallelize 43 pairwise 43 modulated signals 43 mosfet 43 adaptive 43 VHDL code 43 teleology 43 invariance 43 subroutines 43 VxWorks RTOS 43 #:#:# RGB 43 SNMP traps 43 contextual cues 43 PIC microcontroller 43 LX#T FPGA 43 programmable clocks 43 parameterized cells 43 multiprocessor architecture 43 Verilog 43 pipelined architecture 43 Stratix III FPGAs 43 NI LabView 43 APS3 43 dynamical 43 ontologically 43 Actel FPGA 43 IEEE Trans 43 LVCMOS 43 5V supply 43 Simulink 43 #:# LVDS 43 FineSim SPICE 43 CST MWS 43 Darwinian 43 solver 43 VLAN tagging 43 sensorless 43 synchronous asynchronous 43 I2C compatible interface 43 massively parallel architecture 43 RTS CTS 43 Wafer Cone 43 theorization 43 Java runtimes 43 alpha blending 43 #G DQPSK 43 IPSec encryption 43 SAW oscillators 43 datapath synthesis 43 vSwitch 43 supersymmetric 43 dynamically configure 43 #.#Q VLANs 43 nano oscillators 43 coexpression 43 cyclic 43 HardCopy 43 demultiplexers 43 2eSST 43 results QoR 43 mathematical rigor 43 Fractional N 43 pseudowires 43 relational databases 43 parsers 43 datagrams 43 DSP FPGA 43 Switching GMPLS 43 Mode Simulation 43 voltage CMOS 43 Newtonian 43 AdvancedMC module 43 GDSII design 43 compute node 43 MPSoC 43 Newtonian physics 43 sequential clock gating 43 floorplanning 43 epistemic 43 undirected 43 gigabit speeds 43 iterative reconstruction 43 relational 43 Boltzmann 43 throughput 43 dynamically reconfigurable 43 AVR# [002] 43 SS7 ATM 43 iterators 43 #-# mA 43 mask reconfigurable 43 untestable 43 ECVT 43 voiceband 43 voltage #.#V 43 quadrature encoder 43 ARM7 processor 43 Calibre xRC 43 thesis antithesis 43 Synopsys PrimeTime 43 optimizing compiler 43 delta sigma 43 TetraMAX ATPG 43 OC-#/STM-# [002] 43 Boolean expressions 43 literals 43 Proficy Process Systems 43 schema 43 DigRF V4 43 IDT PCIe 43 synchrotron emission 43 pulse widths 43 #Gbs 43 schema validation 43 RLDRAM II 43 Agilent Infiniium 43 Interface MPI 43 DSP BIOS 43 sub picosecond 43 ARM7TDMI processor 43 ARM Cortex M0 43 associative 43 #.#μm CMOS 43 nonparametric 43 Freescale QorIQ P# 43 repeatability 43 syslog 43 PowerTheater 43 ifconfig 43 #K bytes [002] 43 kernel 43 C#x + 43 superluminal 43 SRAM DRAM 43 stateless offload 43 multiscale 43 ZL# device 43 Nios II 43 HDLC 43 table LUT 43 relational OLAP 43 midplane 43 SCPI command 43 Vcc 43 TL1 43 voltage switching ZVS 43 stochastic 43 inferencing 43 jitter clocks 43 GDSII reference 43 pipelining 43 #Msps [001] 43 intuitive graphical 43 traditional SPICE simulators 43 logic solver 43 integrals 43 referential integrity 43 SOAP messages 43 null hypothesis 43 incommensurability 43 cache #KB 43 TDM circuits 43 SOPC Builder 43 op amp 43 ANSI SQL 43 #bit MCUs 43 8MHz 43 LabVIEW graphical 43 multiple equilibria 43 RLDRAM 43 recursively 43 linearization 43 stripline 43 MOS transistors 43 Protocol VRRP 43 IPv6 packets 43 VLIW 43 nonvolatile memory NVM 43 Spread Spectrum 43 DLLs 43 SNMP protocol 43 QUICC Engine 43 inline deduplication 43 chip SoCs 43 neo Darwinism 43 Hegelian dialectic 43 bipolar transistors 43 frequency synthesizer 43 PRBS 43 heterodyne 43 uni directional 43 MSC# DSPs 43 ADC DAC 43 TMS#C#x + DSP 43 address translation NAT 43 multiserver 43 linear equations 43 #.#Gbit s [002] 43 orbital angular momentum 43 #.#V #.#V [001] 43 impedance mismatch 43 integer 43 Mitrion 43 dB SNR 43 PowerQUICC III processor 43 5x #x 43 hierarchical clustering 43 bidirectionally 43 POSIX 43 ROM RAM 43 entropy 43 8PSK 43 Intelli DDR3 43 impedance matching 43 antibody antigen 43 voltage divider 43 embedded microprocessors 43 PECL 43 intelligent caching 43 Actel FPGAs 43 superscalar 43 lambda 43 #.#Gbps [002] 43 optimizations 43 coprocessor 43 FPGA architectures 43 logit 43 CANopen