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(Click for frequent words.) 76 netlists 71 GDSII 70 datapath 67 RTL synthesis 67 parasitic extraction 67 SystemC models 66 PowerPro CG 65 synthesizable 64 DDR PHY 63 VHDL code 63 testbench 63 Talus Vortex 63 testbenches 62 Verilog RTL 62 Magma RTL 62 logic synthesis 62 PowerPro MG 62 equivalence checking 62 Xilinx FPGA 61 CoWare Platform Architect 61 GDSII flow 61 VHDL 61 DRC LVS 61 sequential clock gating 61 Olympus SoC 61 Synplify Premier 61 synthesizable IP 61 Verilog simulation 61 OpenAccess database 61 ISE #.#i 60 SPICE simulator 60 IC Compiler 60 Calibre xACT 3D 60 Design Compiler 60 CellMath IP 60 synthesizable Verilog 60 FPGA fabric 60 Synplify 60 Verilog 60 Encounter Timing System 60 JTAG port 60 IBIS AMI models 60 ANSI C 60 JTAG interface 60 routability 60 IP cores 59 STARCAD CEL 59 FPGA 59 PCell 59 synthesizable RTL 59 algorithmic synthesis 59 ZenTime 59 TRF# [002] 59 SystemC TLM 59 Talus RTL 59 serializer 59 PowerTheater 59 LogiCORE IP 59 Fast Fourier Transform FFT 59 RTL simulation 59 QoR 59 Sequence PowerTheater 59 GDSII design 59 MicroBlaze soft processor 59 Java bytecode 59 SPICE simulation 58 debugger 58 HardCopy II 58 SystemC 58 ESL synthesis 58 parameterized 58 MTCMOS 58 tapeout 58 Blast Create 58 PICO Express 58 Quartz LVS 58 Encounter Conformal Constraint Designer 58 debug 58 parasitics 58 Calibre LFD 58 HDL simulator 58 RealTime Designer 58 Mentor Calibre 58 Xtensa processor 58 SAR ADC 58 DSP algorithm 58 Forte Cynthesizer 58 QuickCap NX 58 datatypes 58 AT#SAM# [002] 58 CAP7 57 structured ASIC 57 Cynthesizer 57 clock gating 57 PCB layout 57 ChipScope Pro 57 LX#T FPGA 57 Quartus II 57 CellMath Designer 57 FineSim SPICE 57 initialization 57 waveform 57 Libero IDE 57 TetraMAX 57 chip variation OCV 57 DSP Builder 57 BIST 57 #b/#b encoding 57 Altera Quartus II 57 TSMC Reference Flow 57 Calibre xRC 57 lithography simulation 57 termination resistors 57 logic analyzer 57 debuggers 57 RealView Profiler 57 boundary scan 57 IP XACT 57 manufacturability DFM 57 SOPC Builder 57 #.#μm CMOS 57 Cadence Encounter 57 coprocessor 57 Cadence QRC Extraction 57 debugging 56 PyCell 56 PLLs 56 Verilog SystemVerilog 56 SPI interface 56 AMBA AXI 56 table LUT 56 Stratix IV FPGA 56 serializer deserializer 56 TSMC AMS 56 PowerArtist 56 CoFluent Studio 56 SoC designs 56 floorplanning 56 Cadence Virtuoso 56 AVR ONE 56 waveform viewer 56 OrCAD 56 Catapult C 56 CustomSim 56 PRBS 56 MicroBlaze 56 XMP metadata 56 Xilinx ML# 56 I2C interface 56 toolpaths 56 deep sub micron 56 results QoR 56 DFT MAX 56 #:# LVDS 56 external EEPROM 56 Altera FPGA 56 YieldAssist 56 adaptive equalization 56 SoC Encounter 56 FineSim Pro 56 Synopsys Galaxy 56 HardCopy ASIC 56 serializer deserializer SerDes 56 Talus Design 56 IC Validator 56 Xtensa LX 56 SiliconSmart 56 HIT Kit 56 SoC Designer 55 Synplify Pro 55 Synplify Pro software 55 Incisive Enterprise 55 multirate 55 synchronous rectifier 55 FPGA prototyping 55 embOS 55 Reference Flow 55 HSPICE 55 uClinux 55 iterator 55 MPLAB 55 DesignWare Verification IP 55 Magma Talus 55 PSpice 55 parameterized cells 55 Fractional N 55 RocketDrive 55 UMC #nm 55 fpgas 55 mosfet 55 lowpass filter 55 Xtensa LX processor 55 Xtensa processors 55 ispLEVER 55 FPGA ASIC 55 TestKompress 55 AVR# [002] 55 memory BIST 55 MPLAB ICD 3 55 MOS transistor 55 Simulink 55 PSoC Designer 55 Active HDL 55 Xilinx ISE 55 SystemRDL 55 EEPROM 55 ARM AMBA 55 Calibre DFM 55 eVC 55 TSMC #nm [001] 55 CoolTime 55 Altera Stratix II 55 FXT FPGAs 55 Nexxim 55 kDiagnostics 55 BSDL files 55 Theseus Titanium 55 PowerCentric 55 Quartus II software 55 JFET 55 level synthesis HLS 55 Design Compiler Graphical 55 Cortex M1 processor 55 NanoTime 55 MicroBlaze processor 55 ProASIC Plus 55 Blast Fusion 55 XSD 55 IPexpress 55 Fast SPICE 55 deserializer 55 CellMath 55 CoWare SystemC 55 CoreMP7 55 CMOS logic 54 Stratix II FPGA 54 ConvergenSC 54 GoldTime 54 EM simulation 54 Bezier curves 54 LUTs 54 DPLL 54 VHDL AMS 54 uC 54 ASIC SoC 54 Virtex 5 54 nanoPHY IP 54 PHY# [001] 54 optimizations 54 deep submicron 54 VisualSim 54 XPath 54 Lattice Diamond 54 TSMC #nm process 54 PIC microcontroller 54 ASIC prototyping 54 AXI TM 54 jitter measurement 54 decoupling capacitance 54 toolchain 54 XML parser 54 serdes 54 ZeBu Server 54 HSIM 54 Stratix III 54 Ansoft Designer 54 Atrenta SpyGlass 54 optimizing compiler 54 Debug 54 JTAG 54 Cadence Incisive 54 Solido Variation Designer 54 multi threaded architecture 54 FPGA synthesis tools 54 EDA tools 54 fast Fourier transform 54 IC Compiler #.# 54 PHY 54 SystemVue 54 VHDL Verilog 54 #.# micron CMOS 54 nvSRAM 54 DFM DFY 54 SPICE simulators 54 Stratix III FPGAs 54 5V CMOS 54 memory subsystem 54 Debugger 54 AMIS # 54 virtual prototyping 54 PECL 54 PrimeTime SI 54 partial reconfiguration 54 schematic capture 54 Synplify DSP 54 Actel FPGA 54 PHY layer 54 programmable OTP 54 Star RCXT TM 54 PSoC Express 54 #b/#b [001] 54 Sourcery + 54 TTL compatible 54 DLLs 54 Cortex M1 54 Synplicity Synplify Pro 54 Arria GX FPGAs 54 PCells 54 RocketIO TM 54 ADCs DACs 54 LEF DEF 54 subroutine 54 ARM7 54 FIFOs 54 BSDL 54 #bit MCUs 54 NexusRoute 54 Agilent J BERT 54 XRT#L# 54 impedances 54 RET OPC 54 ARM Cortex M3 53 XSL FO 53 CMOS RF transceiver 53 DAC# 53 RISC microprocessor 53 MPC# processor 53 PureTime 53 IAR Embedded Workbench 53 CAD geometry 53 XOR 53 MCMM 53 decoupling capacitors 53 demodulation 53 ATmega#P [001] 53 Synopsys IC Compiler 53 bit PIC# MCUs 53 ZeBu 53 #Kbyte [002] 53 MIPS# architecture 53 AFS Nano 53 CMOS compatible 53 Mitrion C 53 CoWare Virtual Platform 53 customizable dataplane processor 53 Spartan 3A 53 Talus Vortex FX 53 nm CMOS 53 pipelined architecture 53 CPLD 53 CO# [001] 53 ARM#EJ S processor 53 Calibre nmDRC 53 Synopsys PrimeTime 53 LVDS outputs 53 XPath expressions 53 LM#S# [002] 53 FPGA designers 53 Parasitic Extraction 53 SystemVerilog verification 53 #MIPS [002] 53 cmos 53 rotary encoder 53 reticle enhancement 53 SiliconSmart ACE 53 Cortex M0 53 SRAM DRAM 53 dsPIC DSC 53 #nm immersion lithography 53 AdvancedMC module 53 checksum 53 System Verilog 53 NI TestStand 53 AMBA protocol 53 MMAV 53 HCS# 53 compiler linker 53 capacitances 53 1Mbyte 53 bit RISC processor 53 Nios II processor 53 bytecodes 53 SAM#G# 53 Silego 53 silicon debug 53 SIwave 53 Reference Methodology 53 parallelization 53 NI Multisim 53 #.#μm [002] 53 #MS s [002] 53 FPGA prototypes 53 Impinj AEON 53 EEPROM memory 53 AVR MCU 53 sensorless 53 SystemC modeling 53 OpenDFM 53 deterministic jitter 53 PIC#F# [001] 53 MAXQ# 53 PCIe Gen2 53 protocol stack 53 MAX# [001] 53 custom ASICs 53 RISC processor 53 Cortex M3 53 Memory Controller 53 AVR Studio 53 Nios II 53 electromagnetic simulation 53 Esterel Studio 53 demux 53 PICO Extreme 53 embedded EEPROM 53 XSLT stylesheets 53 HSPICE R 53 microcontroller 53 loopback mode 53 8bit MCUs 53 EEPROMs 53 locked loop PLL 53 TCI# 53 compiler debugger 52 Evaluation Kit 52 RTL verification 52 SerDes 52 compiler assembler 52 Precision Synthesis 52 Quartz DRC 52 ModelSim 52 EMPro 52 LVTTL 52 threshold voltages 52 AWG# 52 Boundary Scan 52 STA# [001] 52 VTOC 52 AccelDSP 52 XSLT transformations 52 Encounter RTL Compiler 52 uC OS 52 RedHawk SDL 52 CryptoMemory 52 postprocessing 52 Stratix II FPGAs 52 silicon interposer 52 Macraigor 52 mask ROM 52 voltage CMOS 52 Synopsys DesignWare 52 Xilinx FPGAs 52 geometry shaders 52 alpha blending 52 Serdes 52 IO Link 52 x4 PCI Express 52 Specman Elite 52 inductor synthesis 52 Synphony HLS 52 arrays FPGA 52 PCR primer 52 Zroute 52 simultaneous multithreading 52 LatticeSC 52 FPGA synthesis 52 LatticeECP2 M 52 XMEGA 52 EEPROM emulation 52 PrimeYield 52 N#B [001] 52 instantiated 52 ARM Cortex M0 52 modules EVMs 52 Virtuoso IC 52 SoC 52 DataTable 52 SLEC System 52 SCE MI 52 WiCkeD 52 RXAUI 52 Atmel AVR# 52 FBDIMM 52 2KB 52 interprocess communication 52 equivalence checker 52 LVDS output 52 pulse width modulation 52 cache coherency 52 Blackfin BF#x 52 ZMD# 52 compiler optimizations 52 workcell 52 TMS#DM# [001] 52 DataSet 52 Verix 52 deterministically 52 raster image 52 serial EEPROMs 52 bitmaps 52 DXF 52 PIC#F# [002] 52 verification signoff 52 parametric 52 #.#V CMOS 52 decoupling capacitor 52 Actel ProASIC3 52 IBIS AMI 52 Actel FPGAs 52 hardware accelerators 52 associativity 52 downconverter 52 RapID Platform 52 ADC DAC 52 DMOS 52 PICO Extreme FPGA 52 root filesystem 52 LVCMOS 52 SPI#.# 52 linearization 52 kit RDK 52 ProASIC3 FPGAs 52 XS1 G4 52 SystemC simulation 52 de interlacing 52 thresholding 52 PID loop 52 LDRA Testbed 52 embedded processor cores 52 datapaths 52 6WINDGate 52 HyperView 52 OpenAccess 52 XML parsing 52 RapidChip 52 IXP# [001] 52 hardware abstraction layer 52 FPGA CPLD 52 vectorless 52 impedance measurements 52 programmability 52 FmPro Migrator 52 PHY interfaces 52 IC CAP 52 Blackfin Processors 52 FPDP 52 PWM signal 52 uCLinux 52 HardCopy 52 IQ modulator 52 ARM# [003] 52 EDID 52 bytecode 52 Magma Blast 52 C# DSP 52 NanoSim 52 F#x [001] 52 ANX# 52 integrating NVM 52 IAR KickStart Kit 52 nm CMOS process 52 ARChitect 52 Mentor Questa 52 EPROM 52 GN# [002] 52 PCIX 52 DMA controller 52 SERDES 52 executable specification 52 QT# [001] 52 XIO# 52 ARM7TDMI processor 52 kit PDK 52 postprocessor 52 electrically erasable programmable 52 Cadence Allegro 52 Bitmap 52 OCP socket 52 linearisation 52 Stratix II GX 52 RealView SoC Designer 51 #Kbytes [002] 51 RISC cores 51 TLM#.# 51 toolsuite 51 VarioTAP 51 RS# interface 51 RTL Compiler 51 parsers 51 linearized 51 Regular Expression 51 FPGA implementations 51 TMS#DM# [002] 51 Agility Compiler 51 Star RCXT 51 Synopsys DesignWare ® 51 #nm FPGAs 51 ATA# [002] 51 malloc 51 chip SoCs 51 interposer 51 #Mbyte [001] 51 pinout 51 fpga 51 Stratix GX 51 FinFET 51 BPEL processes 51 FPGAs 51 Nios processor 51 binary executable 51 PHYs 51 Flash MCU 51 MemoryScape 51 Altera FPGAs 51 Cortex M4 processor 51 RC oscillator 51 jitter tolerance 51 CPU emulation 51 Allegro PCB 51 OpenMP 51 Mazatrol 51 macroblock 51 InCyte 51 ASICs 51 Texas Instruments OMAP# 51 DXF file 51 SGMII 51 Xilinx Spartan 3A 51 JTAG debug 51 SpyGlass Power 51 synchronous Ethernet 51 eSi 51 MATLAB algorithms 51 VHDL simulation 51 memory compilers 51 PCRE 51 Agilent ADS 51 Aceplorer 51 ADSP BF# 51 MIPS cores 51 DFEB 51 Synopsys DFM 51 OpenArbor 51 metamodel 51 configurable 51 Virtuoso Accelerated Parallel Simulator 51 syntax highlighting 51 Vertex Shader 51 fully synthesizable 51 SAM3U 51 JSPs 51 XMC module 51 PyCells 51 WebForms 51 initialisation 51 graphical debugging 51 Altium Designer 51 tables LUTs 51 Actel Fusion 51 waveforms 51 MathWorks Simulink 51 SystemWeaver 51 ARM#EJ processor 51 DLL 51 Evaluation Module 51 Xilinx Virtex 5 51 arbitrary waveform 51 multi Vdd 51 AVR microcontrollers 51 pinouts 51 Spartan 3E 51 PolarPro 51 Differential Signaling 51 TreeView 51 E#A [002] 51 MPC#E processor 51 microcode 51 parameterisation 51 XML Schema 51 VMMK #x# 51 daughtercards 51 TBrun 51 #nm node [002] 51 HDL Designer 51 ADRES 51 arbitrary waveform generators 51 Cadence Encounter RTL Compiler 51 Vdd 51 DSP FPGA 51 ARM7 processor 51 stripline 51 BLDC motor 51 external resistor 51 simulator debugger 51 JTAG debugger 51 PCI Express PHY 51 XML metadata 51 Simics 51 Preconfigured 51 baud rate 51 coprocessing 51 PureSpec 51 1dB 51 MPC#E 51 LNAs 51 complex SoC designs 51 preprocessor 51 8KB 51 AVR microcontroller 51 ARM9 core 51 Verilog VHDL 51 Silicon Compiler 51 STR#F 51 datapath designs 51 MOSFETS 51 compilers debuggers 51 Prover eCheck 51 serializers 51 XAUI 51 embedded SRAM 51 kbyte 51 transimpedance amplifier 51 ARM# [001] 51 synchronous MOSFET 51 jitter attenuation 51 AccelChip 51 web.config file 51 op amp 51 ARM#JZF S processor 51 clockless 51 Trueflow SE 51 parametrically 51 AutoCAD DWG 51 wirebond 51 iRCX 51 vNIC 51 L1 cache 51 LXT FPGAs 51 interleaving 51 Javadoc 51 ODBC compliant database 51 Multi threading 51 ASIC FPGA 51 array FPGA 51 SAW filter 51 Mentor Graphics ModelSim 51 Cadence Encounter digital 51 graphical debugger 51 ProASIC3 E 51 x8 PCI Express 51 Lattice FPGAs 51 SystemC transaction 51 ColdFire 51 LINQ queries 51 LTC#/-# 51 precompiled 51 Agilent #A [001] 51 Lauterbach TRACE# 51 Verific 51 ratiometric 51 IEnumerable 51 Application Specific Integrated 51 Digital Converter ADC 51 8bit MCU 51 DSP BIOS 51 XML schema 51 EXIF metadata 51 respins 51 #Kbyte [001] 51 raster images 50 SerDes chipset 50 i.MX# [001] 50 MPC# [003] 50 IEEE #.# [002] 50 structured ASICs 50 macros 50 asymmetric multiprocessing 50 RISC DSP 50 Platform FPGAs 50 #Gbit [001] 50 SmartSpice 50 LVDS interface 50 ADC#D# 50 voltage differential 50 GDSII reference 50 consumes #mW 50 computationally efficient 50 crystal oscillator 50 Mentor Graphics Calibre 50 MIPS processor 50 MPEG encoder 50 datapath synthesis 50 LGS 2D 50 schematics layout 50 ProASIC3 50 AMBA AHB 50 Agilent U#A 50 digital converter ADC 50 Quartz 2D 50 TCP IP stack 50 SOAP messages 50 Logic Navigator 50 synchronous buck converter 50 FPGA DSP 50 Mode Simulation 50 nm nodes 50 DesignWare Verification Library 50 instrumentation amplifier 50 testability 50 μsec 50 protocol stacks 50 modulation formats 50 Actel flash 50 #Kf 50 CAN transceiver 50 RFXpress 50 PowerPro Analyzer 50 CS#L# 50 LatticeECP2M 50 CharFlo Memory 50 MAX# [003] 50 datasheet 50 Blackfin processor 50 ChIP Seq 50 Cadence Silicon Realization 50 ispLEVER design 50 Posix 50 ARM#T 50 Verilog HDL 50 ARM RealView 50 Customizable Microcontroller 50 Tessent 50 parameterization 50 SDI inputs 50 C Compiler 50 IEEE#.# [002] 50 Memory Controllers 50 #nm RF CMOS 50 buck converter 50 SiWare 50 parametrics 50 NanoBoard 50 quantization 50 Cadence Palladium 50 3D LUTs 50 Virtex II 50 symmetric encryption 50 #.#Gbps [003] 50 HyperLynx 50 #ns [002] 50 #.#μm CMOS process 50 Nucleus OS 50 Crossware 50 correction OPC 50 pin BGA package 50 Stratix IV E 50 MPLAB IDE 50 RS#/RS# 50 PCIe specification 50 VCS Verification Library 50 GHz RF transceiver 50 Serial Analyzer 50 simulated annealing 50 EEMBC benchmarks 50 LatticeECP3 ™ 50 DM# [001] 50 Simulink models 50 Polyhedra 50 multiply accumulate 50 GCC compiler 50 TI TMS#C# 50 coupling capacitors 50 VarioTAP ® 50 I2C serial interface 50 quadrature encoder 50 ARM#JF S 50 MCP# AFE 50 NOR NAND 50 TetraMAX ATPG 50 zener diode 50 ATR# [002] 50 JTAGICE mkII 50 MAX#/MAX# [002] 50 MPLAB ICD 2 50 ASIC ASSP 50 dsPIC DSCs 50 #v# [004] 50 DesignWare USB 50 serial EEPROM 50 Stratix II GX FPGA 50 Nios II Compiler 50 DDR2 DRAM 50 arbitrary waveform generator 50 Hardware Description Language 50 arbitrary waveforms 50 I2C compatible 50 SMSC USB# 50 I2C bus 50 UltraLightClient 50 waveform generator 50 uC OS III 50 ColdFire architecture 50 SystemVerilog 50 GX FPGA 50 MCF# 50 #.#um [002] 50 JavaScript DOM 50 XSLT transformation 50 ACCELLERANT 50 deterministic 50 Graphical User Interface GUI 50 quadrature modulator 50 #/#-bit [002] 50 NVRAM 50 CircuitSpace 50 DSP algorithms 50 VMM methodology 50 MB#R# 50 RocketIO 50 UCC# 50 curve tracer 50 prefetch 50 PID controller 50 SystemVue #.# 50 ARM#EJ S 50 nondeterministic 50 bypass capacitor 50 PowerShell commands 50 Array FPGA 50 Cadence Virtuoso custom 50 NetX Duo 50 MAX# MAX# [001] 50 ARM#EJ S TM 50 reprogrammable 50 CoreSight 50 MPLAB REAL ICE 50 DDR3 modules 50 ARM Artisan 50 DIMM modules 50 FreeRTOS.org 50 dsPIC 50 SDI outputs 50 dsPIC#F 50 Quick Path Interconnect 50 #bit [001] 50 z axis 50 5 LXT 50 uPD# [001] 50 AVR# Studio 50 JavaServer Pages JSP 50 single external resistor 50 MIPS# #K 50 Structured ASIC 50 Kbits 50 LatticeEC 50 VisualDSP + + 50 Embed X 50 parameterised 50 NURBS 50 geometric distortion 50 DWF files 50 Xilinx Embedded 50 TekExpress 50 multibit 50 Multithreaded 50 Virtuoso Multi 50 SSIS packages 50 AMBA Designer 50 JBIG2 50 nanometer silicon 50 automatically configures 50 PrimeYield LCC 50 #bit ADC 50 ARM#E 50 Parameter 50 DSP BIOS TM 50 TimeSys Linux 50 Nios II embedded 50 characteristic impedance 50 demultiplexer 50 SCADE 50 finite element method 50 VCXO 50 Serial Peripheral Interface SPI 50 TCP IP networking 50 RLDRAM 50 sampling oscilloscope 50 #:# multiplexer 50 Makefile 50 code refactoring 50 anti aliasing filters 50 parser 50 GLOBALFOUNDRIES #nm 50 SPICE accuracy 50 Kilopass XPM 50 BCSM# 50 Measurement Studio 49 subsystem 49 charset