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(Click for frequent words.) 67 routability 62 parametric yield 60 parasitic extraction 60 memory BIST 59 BIST 59 Design Compiler Graphical 58 equivalence checking 58 boundary scan 58 QoR 57 PHY layer 57 reconfigurability 57 co planarity 57 NanoTime 57 respins 57 Stratix III FPGAs 57 DFT MAX 57 manufacturability 56 Actel FPGAs 56 deep submicron 56 PCB layout 56 JTAG port 56 algorithmic synthesis 56 GDSII flow 56 Deterministic 56 logic synthesis 56 DDR PHY 56 CustomSim 56 IC Validator 56 Synopsys Galaxy 56 partial reconfiguration 55 Boundary Scan 55 manufacturability DFM 55 JESD# [002] 55 loopbacks 55 SPICE simulation 55 datapath 55 Tessent 55 results QoR 55 SerDes 55 SPICE simulator 54 electromagnetic compatibility EMC 54 DfM 54 electromigration 54 synchronous Ethernet 54 ZenTime 54 testbench 54 CAN transceiver 54 serializer deserializer 54 galvanic isolation 54 multi Vdd 54 IBIS AMI 54 TetraMAX 54 PowerTheater 54 vectorless 53 structured ASICs 53 ISE #.#i 53 Manufacturability 53 solderability 53 Vdd 53 CoolTime 53 compiler optimizations 53 Encounter Timing System 53 Serdes 53 Cadence Encounter 53 SyncE 53 jitter measurement 53 sequential clock gating 53 JTAG boundary scan 53 IEEE #.# [002] 53 noise ratio SNR 53 termination resistors 53 loopback mode 53 testbenches 53 kit PDK 53 PowerPro MG 53 impedance measurements 53 multibit 53 Precision Synthesis 53 HyperLynx 53 PCI Express specification 53 SPICE simulators 53 programmability 53 Stratix II FPGAs 53 Bit Error Rate 53 SystemC models 53 silicon debug 53 datapath synthesis 52 Encounter RTL Compiler 52 TetraMAX ATPG 52 MAX# integrates 52 floorplanning 52 PHYs 52 LDRA Testbed 52 HSIM 52 finite element modeling 52 voiceband 52 SynTest 52 electromagnetic compatibility 52 TestKompress 52 YieldAssist 52 parameterisation 52 deterministic jitter 52 FPGA prototyping 52 threshold voltages 52 MCP# AFE 52 latency jitter 52 DPOJET 52 CellMath Designer 52 jitter tolerance 52 Calibre xACT 3D 52 FPGA synthesis tools 52 ITU T Y.# 52 CPU emulation 52 RF Microwave 52 interrupt latency 52 SoC designs 52 complex SoC designs 52 overvoltage protection 52 SDH SONET 52 SPICE accuracy 52 FPGA ASIC 52 Optimizations 52 PureTime 52 SAR ADC 52 SFP + module 52 IEEE #.# JTAG 52 PowerArtist 52 SIwave 52 DRC LVS 52 Memory Controllers 52 SystemVerilog verification 52 dv dt 52 Xtensa processor 52 EUV mask 52 DSP algorithm 52 ETMemory 52 voltage CMOS 51 memory compilers 51 chip SoCs 51 Arria GX FPGAs 51 #.#ag 51 Stratix II devices 51 ZSN 51 stackup 51 PIN diodes 51 DesignWare IP 51 serializer deserializer SerDes 51 TJA# 51 Inductance 51 5V CMOS 51 Infiniium oscilloscopes 51 singulation 51 coplanarity 51 electromagnetic interference EMI 51 overcurrent protection 51 FPGA designers 51 serdes 51 System Verilog 51 PowerPro CG 51 Nios II Compiler 51 overtemperature protection 51 backplane traces 51 GDSII 51 debug 51 Stratix II FPGA 51 MS#A 51 analog circuits 51 stripline 51 Stratix IV FPGA 51 Sequence PowerTheater 51 Talus Design 51 power dissipation 51 PID loop 51 OSNR 51 fpgas 51 AMS RF 51 8bit MCU 51 embedded processor cores 51 Repeatability 51 HardCopy ASIC 51 serial interfaces 51 SOPC Builder 51 daughtercards 51 interleaving 51 ARM7TDMI processor 51 MCMM 51 AWG# 51 deep sub micron 51 loopback 51 SystemC modeling 51 integrating NVM 50 datapath designs 50 Serializer Deserializer 50 TSMC Reference Flow 50 cache coherency 50 tapeout 50 optimization algorithms 50 HSPICE R 50 packet jitter 50 Olympus SoC 50 Vcore 50 parasitics 50 Talus Vortex 50 debugging tools 50 RTL synthesis 50 ownership CoO 50 Atrenta SpyGlass 50 Manufacturability DFM 50 Fast Fourier Transform FFT 50 netlist 50 Encounter Conformal Constraint Designer 50 #nm FPGAs 50 code refactoring 50 AEC Q# qualified 50 Power Format UPF 50 PCIe Gen2 50 Talus RTL 50 Nios II 50 Cortex R4F processor 50 reliability 50 OpenAccess database 50 Actel flash 50 OTDRs 50 computational complexity 50 Xilinx FPGAs 50 RFIC simulation 50 level synthesis HLS 50 Altera Stratix II 50 chip SoC designs 50 impedance matching 50 Optixia 50 synchronous rectifier 50 ASIC SoC 50 FD SOI 50 clock gating 50 performance serial BERT 50 LabVIEW graphical 50 Cortex R4 processor 50 ASIC prototyping 50 IEC #-# [001] 50 RFI EMI 50 serializers 50 Anirudh Devgan general 50 Blackfin Processors 50 SiliconSmart 50 ProASIC3 FPGAs 50 Flash EEPROM 50 DevPartner Fault Simulator 50 Impinj AEON 50 ceramic capacitor 50 GoldTime 50 SLC NAND flash 50 metastability 50 scales linearly 50 di dt 50 checkpointing 50 analog circuitry 50 Synopsys PrimeTime 50 PowerTheater Explorer 50 Ethernet AVB 50 optical interconnect 50 Alien Crosstalk 50 ARM AMBA 50 XFP module 50 #v# [004] 50 capacitances 50 optical spectrum analyzers 50 linearization 50 datarates 50 HardCopy II 50 USB PHY 50 singlemode 50 E StaX 50 ANSYS POLYFLOW 49 Quartus II 49 adaptive equalization 49 tolerancing 49 macrocell 49 mode dispersion PMD 49 parametrics 49 Keithley RF 49 IBIS AMI models 49 defectivity 49 planarity 49 TMDS 49 jitter wander 49 uC 49 reliabilities 49 SERDES 49 MBd 49 dielectric breakdown 49 DUTs 49 XAUI 49 Xtensa LX processor 49 GDSII reference 49 Altera Quartus II 49 Synopsys DesignWare 49 Calibre nmDRC 49 IntelliMAX 49 Nios processor 49 curve tracer 49 jitter attenuation 49 EDA tools 49 latency packet 49 Actel Fusion 49 schema validation 49 MIPS CPU 49 decoupling capacitance 49 ANSI C 49 Spirent Avalanche 49 Marvell #W# 49 parasitic capacitances 49 observability 49 CMOS transistors 49 Fractional N 49 SoC verification 49 Synplify Premier 49 nvSRAM 49 MicroBlaze processor 49 Rockwell Automation Integrated 49 accuracy repeatability 49 CellMath IP 49 digital isolators 49 reproducibility 49 multiplexing capability 49 digital multimeters 49 Spirent TestCenter 49 CFP MSA 49 finite element method 49 FPGA architectures 49 mux demux 49 input capacitance 49 geometries shrink 49 multicore DSP 49 UMC #nm 49 APx 49 synchronous buck converter 49 Xgig 49 AVR ONE 49 Y.# 49 Calibre DFM 49 FastSPICE 49 parasitic capacitance 49 design kits PDKs 49 Watchdog Timer 49 topology 49 Evaluation Module 49 op amp 49 synthesizable IP 49 #Base T [002] 49 spectral density 49 IPSec encryption 49 differential impedance 49 Sonet SDH 49 programmable OTP 49 Wafer Cone 49 MTS# 49 Virtuoso AMS Designer 49 Simulink models 49 thermal impedance 49 XMEGA 49 thermal dissipation 49 RF amplifier 49 inferencing 49 CAN LIN 49 IEEE #v# 49 VLAN tagging 49 XFP modules 49 #G CFP 49 RFC# 49 Synplify Pro software 49 Symantec i3 49 jitter measurements 49 Digital Converter ADC 49 PHY# [001] 49 MPC#E processor 49 SCE MI 49 Xilinx ISE 49 linearly scalable 49 leakage currents 49 ProASIC3 devices 49 ASIC FPGA 49 SystemC simulation 49 Spirent TestCenter HyperMetrics 49 VHDL Verilog 49 PlanAhead 49 PureTime ™ 49 Magma RTL 49 rotary encoder 49 #Gbit s Ethernet [002] 49 Stratix II 49 SFP + transceivers 49 AEC Q# automotive 49 overtemperature 49 sampling oscilloscopes 49 DDR3 RDIMM 49 RTL Compiler 49 Antun Domic senior 49 JTAG Boundary Scan 49 ETX #A 49 #-Gbit/sec 49 Prover eCheck 49 external EEPROM 49 IEEE#.# [002] 49 ASICs 49 ADuM# 48 digital isolator 48 protocol conformance 48 L2 L7 48 4kV 48 multirate 48 CAN transceivers 48 Calibre xRC 48 SmartFusion devices 48 ZigBee mesh 48 #GBASE CX4 48 alien crosstalk 48 modularity 48 HSPICE 48 Questa verification 48 Magnum 2x 48 NanoSim 48 #.#VI O 48 jitter latency 48 IxANVL 48 Encounter Conformal 48 upgradeability 48 ASSET ScanWorks 48 arrays FPGA 48 Solido Variation Designer 48 baseband processing 48 CMOS ICs 48 SpyGlass ® 48 MirrorBit NOR 48 LabVIEW graphical programming 48 SOAPSonar 48 VarioTAP 48 dc dc conversion 48 computational fluency 48 Verix 48 emPROM 48 PROFIBUS PA 48 SFDR 48 Hardware Description Language 48 MT#B [001] 48 Autosar 48 FineSim SPICE 48 modulation schemes 48 Proficy HMI SCADA iFIX 48 lambdas 48 Zroute 48 #bit MCUs 48 characteristic impedance 48 Design Compiler 48 FPGA implementations 48 LAN# 48 AMBA AXI 48 Quartus II software 48 multigigabit 48 voltage #.#V 48 GX FPGA 48 weatherability 48 SoCs ASICs 48 parallelizing 48 interrater 48 EMI electromagnetic interference 48 Fast SPICE 48 FineSim Pro 48 AXI TM 48 magnetic rotary encoder 48 decoupling capacitors 48 MirrorBit ORNAND 48 EM simulation 48 FastScan 48 simulated annealing 48 SerDes chipset 48 bypass capacitor 48 SPI#.# 48 transimpedance 48 PHY 48 Cadence SoC Encounter 48 GPIB interface 48 SFP + modules 48 NBTI 48 Axcelerator 48 parallelization 48 RF baseband 48 PID controller 48 MOS transistor 48 respin 48 Actel FPGA 48 SignalExpress 48 #:# LVDS 48 SoC Encounter 48 packetization 48 embOS 48 TCP UDP 48 ESL synthesis 48 Reference Verification Methodology 48 NI TestStand 48 O subsystem 48 LLDP MED 48 Serial RapidIO IP 48 Quartz LVS 48 MSC.Patran 48 jitter 48 nMOS 48 μsec 48 BGA packaging 48 SOC designs 48 #G/#G [001] 48 stateful failover 48 MicroBlaze 48 ADSL/ADSL2 + 48 maintaining backwards compatibility 48 inferential statistics 48 finite element solver 48 MATLAB ® 48 JESD#A 48 Xtensa processors 48 XJTAG boundary scan 48 extendibility 48 #GFC 48 PCell 48 Passive Optical Networks 48 ADC DAC 48 Gigabit Ethernet #GE 48 sampling oscilloscope 48 thresholding 48 arbitrary waveform generators 48 Shenick diversifEye 48 embedded EEPROM 48 voltage derating 48 IPsec SSL 48 VCXOs 48 #b/#b encoding 48 FPGA 48 Agilent DisplayPort 48 FPGA CPLD 48 PLL Noise Analyzer 48 Kaminario K2 48 CoreMP7 48 NVMs embedded memory 48 echo canceller 48 Gigabit Ethernet transceivers 48 muxing 48 multipath fading 48 netlists 48 optical modulation analyzer 48 8kV 48 MasterClaw 48 Star RCXT 48 TCP acceleration 48 repeatable measurements 48 PLDs 48 MirrorBit Eclipse 48 warpage 48 NightStar tools 48 crosstalk cancellation 48 C#x DSPs [001] 48 TestPoint 48 CAPEX OPEX 48 IGMP snooping 48 IC Compiler 48 instrumentation amplifier 48 nm CMOS 48 wirespeed 48 spectral efficiency 48 SiWare 48 PCIe GbE 48 Stratix II GX 48 MOSFETS 48 CoCreate Modeling 48 Synopsys IC Compiler 48 converter topology 48 PowerCentric 48 asynchronous messaging 47 Atmel ATmega#RFA# 47 SiliconSmart ACE 47 tapeout schedules 47 Calibre LFD 47 TCI# 47 CoWare ESL 47 TCP throughput 47 executable specification 47 SCADE 47 falsifiability 47 backplane 47 serial RapidIO 47 Bidirectional 47 8GFC 47 multithread 47 multi pathing 47 HIT Kit 47 eNB 47 RAID adapters 47 reprogrammability 47 GZIP compression 47 robustness 47 QSFP connector 47 milliohm 47 PIC microcontroller 47 VHP# 47 multiplexing capabilities 47 CMOS logic 47 IRS#D 47 ADI AD# 47 EasyPath 47 op amps 47 multicore architecture 47 FPGA prototypes 47 snubber circuits 47 MODBUS 47 NCV# 47 LatticeECP3 47 pinout 47 eVC 47 InfiniBand interconnects 47 acoustic echo canceller 47 loopback testing 47 OADMs 47 FPGA synthesis 47 ATmega#P [001] 47 operational amplifiers 47 impedances 47 timebase 47 XBee PRO ZB 47 linearity 47 DSPs FPGAs 47 reverse polarity protection 47 crosspoint 47 HyperLynx PI 47 PCI Express Serial ATA 47 waveform generator 47 VOUT 47 electro magnetic interference 47 iRCX format 47 T1 E1 47 VMM methodology 47 Signal Analyzer 47 Rdson 47 Calibre PERC 47 #BASE T [001] 47 Multimeter 47 Verilog RTL 47 optocoupler 47 demodulation 47 QuickCap NX 47 interobserver 47 RET OPC 47 Virtex 5 47 debugging 47 SoC 47 phonics fluency vocabulary 47 serial EEPROM devices 47 transmit beamforming 47 Forte Cynthesizer 47 coded RTL 47 #kV ESD 47 UltraWave #G 47 JTAG interface 47 Measurement Studio 47 regulator LDO 47 ATTO Disk Benchmark 47 Model #A 47 Cadence Encounter digital 47 please visit www.EXFO.com 47 Mixed Signal IC 47 intelligently integrates 47 ARM Cortex M0 47 x4 PCI Express 47 capacitive loading 47 ChipScope Pro 47 SRAM DRAM 47 Valor DFM 47 backplane connector 47 parasitic inductance 47 SmartPlant Electrical 47 temperature coefficients 47 PrimeYield 47 correction OPC 47 local oscillator LO 47 datapaths 47 MACsec 47 IC Compiler #.# 47 parameterization 47 test DUT 47 Electromagnetic Interference EMI 47 Video Coding SVC 47 Nios II processor 47 Aceplorer 47 Nexxim 47 transconductance 47 voltage MOSFET 47 ESD protection 47 virtual prototyping 47 Xilinx Spartan 3A 47 lowpass filter 47 VCXO 47 tighter tolerances 47 linearisation 47 failover failback 47 1T FLASH 47 Synopsys DesignWare ® 47 interconnect capacitance 47 microstrip 47 Ixia IxNetwork 47 ArctiCore 47 ADIS# 47 domain reflectometry TDR 47 Revit BIM 47 jitter packet loss 47 HCS# 47 throughput 47 Agilent N#B 47 DSP BIOS 47 Agilent Infiniium 47 wafer uniformity 47 Open Verification Methodology 47 optimality 47 output impedance 47 Cadence Virtuoso custom 47 Cortex M3 core 47 MOSFET gate 47 1uA 47 Synplify DSP 47 parametric 47 Analog ICs 47 #X# MIMO 47 moisture ingress 47 #MIPS [002] 47 MSP# MCU 47 Debug Solution 47 oxide thickness 47 MPSoC 47 echo cancellers 47 instrumentation amplifiers 47 Reproducibility 47 #GB/sec 47 connectorization 47 CPLD 47 FPGAs 47 fault tolerant computing 47 geometric modeling 47 SAW filter 47 repeatability 47 Cadence Virtuoso 47 Physical Verification 47 conformance testing 47 SONET SDH OTN 47 motor windings 47 H VPLS 47 operability 47 BSDL files 47 RF circuitry 47 bipolar transistors 47 logic analyzers 47 mosfet 47 Spanning Tree 47 Coverity Prevent 47 external resistor 47 FBDIMM 47 TCP protocol 47 Magma Talus 47 repair MTTR 47 backplanes 47 FPGAView 47 FPGAs CPLDs 47 RF ICs 47 sigma delta ADC 47 scalability 47 Ethernet TCP IP 47 opto coupler 47 adaptive modulation 47 Verilog HDL 47 Codenomicon DEFENSICS 47 EEPROM emulation 47 IxNetwork 47 silicone leakage 47 BJTs 47 Packet Blazer 47 Sercos III 47 combinational 47 EXata 47 RedHawk NX 47 OmniPixel3 HS 47 8GHz 47 B4 Flash 47 PWM pulse width modulation 47 Quartz DRC 47 FPGA fabric 47 Libero IDE 47 Design Kits 47 STR#F 47 nanoPHY IP 47 waveform viewer 47 Tx Rx 47 #GbE switches 47 I2C interface 47 LabWindows CVI 47 voltage switching ZVS 47 IDT PCIe 47 Synplify Pro 47 TMS#DM# [002] 47 SpyGlass Power 47 #Gb s Fibre Channel 47 Ethernet OAM 47 microampere 47 #bit MCU 47 iCoupler 47 SIMD instructions 47 CryptoFlash 47 MILS architecture 47 Optocoupler 47 compiler debugger 47 #.#Ω 47 J BERT 47 CWDM wavelengths 47 RTL verification 47 Pattern Matching 47 StarRC Custom 47 IEEE #.#x [002] 47 baseband MAC 47 SPDT switches 47 decompilation 46 parameter settings 46 external Schottky diode 46 serialiser 46 Parasoft SOAtest 46 RLDRAM II 46 Mosfet 46 MTCMOS 46 5x #x faster 46 AVR microcontroller 46 multipath interference 46 object relational 46 pluggable optics 46 dataplane 46 quantization noise 46 SPICE accurate 46 Agilent N2X 46 Verification Platform 46 Cortex M4 processor 46 signaling conformance 46 SigmaQuad 46 topology mapping 46 HW SW 46 ARM Cortex M3 46 Ethernet MACs 46 pluggable module 46 verification signoff 46 VRRP 46 stochastic simulation 46 SC FDMA 46 stray capacitance 46 LTE UE 46 QualiPHY 46 Die Termination ODT 46 IEEE #.# standard 46 VHDL AMS 46 +5 dBm 46 Verification Methodology 46 temperature coefficient 46 Coleman Liau 46 sRIO 46 AUIRS#S 46 SRIO 46 LVDS outputs 46 SONET EoS 46 Lattice FPGAs 46 feedforward 46 thermal foldback 46 fanout 46 ConvergenSC 46 proactively troubleshoot 46 #pF [001] 46 Emerson PlantWeb digital 46 Xilinx FPGA 46 Tsi#A 46 PSRR 46 SystemC TLM 46 Link OAM 46 3GPP LTE 46 sub microsecond 46 APP# [002] 46 Verification Methodology Manual VMM 46 #ns [002] 46 UltraFLEX 46 defect densities 46 Specman Elite 46 bandpass 46 Synplify 46 Z Foil 46 ARM Artisan 46 TCP optimization 46 Flash Programmer 46 #.#af 46 Gbits s 46 PSoC Express 46 MAX# [001] 46 #G DQPSK 46 VSWR 46 LatticeECP3 ™ 46 nonvolatile memories 46 bi directional communication 46 Ethernet Powerlink 46 Serial RapidIO 46 fast Fourier transform 46 fault tolerant architecture 46 PICO Extreme 46 coprocessing 46 DFM DFY 46 logic solver 46 Cadence Incisive 46 Zarlink ToP 46 IPv6 routing 46 #.#n MIMO 46 MEGACO 46 SiliconDrive 46 SPDT switch 46 output capacitance 46 6LoWPAN 46 datarate 46 IPv#/IPv# 46 PrimeTime SI 46 Electrostatic Discharge ESD 46 moldability 46 Apdex 46 RTL simulation 46 iteratively 46 volumetric efficiency 46 PoE Plus 46 LVPECL 46 Finite Element Method 46 #G/#G Ethernet 46 combinatorial optimization 46 electrically noisy 46 equivalence checker 46 passive intermodulation 46 deterministic 46 Immunodiagnostic System 46 traditional SPICE simulators 46 RSA#B 46 transceiver IC 46 MetroScope 46 Proficy Historian 46 scalability adaptability 46 smaller geometries 46 Solarflare #GBASE T 46 TTL compatible 46 interconnects 46 #/#G [002] 46 2eSST 46 JTAG 46 modulation formats 46 TLM#.# 46 testbench automation 46 spatial temporal 46 Extensible Processing Platform 46 DDR2 memory interface 46 Precision RTL synthesis 46 MIPS# architecture 46 POL converters 46 computational lithography 46 uW 46 IntelliTrace 46 PowerOpt 46 MAX# MAX# [001] 46 MSC# DSP 46 Synopsys Synplify 46 electrostatic discharge ESD 46 optimizing compiler 46 interposer 46 CATIA V5 Composites 46 Testability 46 C#x + 46 QoS Quality 46 model A# 46 voltage MOSFETs 46 QDRII 46 MOS transistors 46 intermodulation distortion 46 + #.#dB 46 DFT 46 optimizations 46 ohmic 46 timestamping 46 Input Voltage 46 bend radius 46 PCIe Gen 2 46 ADA# 46 WAN emulation 46 dephasing 46 Iub 46 BugScope 46 Lavastorm Analytic Platform 46 deviceWISE 46 ReDriver 46 AdvancedMC module